vhdl program for fulladder using structural modelling

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fulladd is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c_in :in STD_LOGIC;
         c_out:out STD_LOGIC;
         sum : out STD_LOGIC
         );
end fulladd;

--}} End of automatically maintained section

architecture fulladd_str of fulladd is

component halfadd is
    port (
    a:in STD_LOGIC;
    b:in STD_LOGIC;
    p_sum:STD_LOGIC;
    p_carry:STD_LOGIC
    );
end component ;     

component or2 is
    port(
    a:in STD_LOGIC;
    b:in STD_LOGIC;
    c_or:out STD_LOGIC
    );
end component ;


    signal s1,s2,s3:BIT;
    begin
       
        x1:halfadd port map (a,b,s1,s2);
        x2:halfadd port map (s1,c_in,sum,c_out);
        x3:or_2    port map (s2,s3,c_out);   
   

     -- enter your statements here --

end fulladd_str;