vhdl program for full adder using dataflow modelling

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--
-- Title       : fulladd
-- Design      : and1
-- Author      : rajashekar
-- Company     : kits
--
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--
-- File        : fulladd.vhd
-- Generated   : Thu Jul 11 13:15:24 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description :
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {fulladd} architecture {fulladd_df}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fulladd is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         cin : in STD_LOGIC;
         ps : out STD_LOGIC;
         pc : out STD_LOGIC
         );
end fulladd;

--}} End of automatically maintained section

architecture fulladd_df of fulladd is
begin
   
    ps <= (a xor b) xor cin;
    pc <= (a and b) or (b and cin) or (a and cin);
   

     -- enter your statements here --

end fulladd_df;