vhdl program for full adder using mux

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_fulladd is
    port (a:in STD_LOGIC_VECTOR (0 to 2);
    s:in STD_LOGIC_VECTOR (0 to 1);
    sum:out STD_LOGIC;
    carry:out STD_LOGIC
    );
end mux_fulladd;


--}} End of automatically maintained section

architecture muxfulladd_arch of mux_fulladd is

component mux_41 is
    port (i0 :STD_LOGIC;
    i1 :in STD_LOGIC;
    i2 :in STD_LOGIC;
    i3 :in STD_LOGIC;
    s:in STD_LOGIC_VECTOR (0 to 1);
    y:out STD_LOGIC
    );
end component ;

signal  cbar:STD_LOGIC;
begin
    process (a,s)
    cbar <= not a(2);
    begin
       
        m1:mux_41 port map (a(2),cbar,cbar,a(2),a(0 to 1),sum);
        m2:mux_41 port map (0,cbar,cbar,1,a(0 to 1),carry);
       
    end process;
end fulladd_arch;