vhdl program for 4x1 mux

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_41 is
    port (i0 :STD_LOGIC;
    i1 :in STD_LOGIC;
    i2 :in STD_LOGIC;
    i3 :in STD_LOGIC;
    s:in STD_LOGIC_VECTOR (0 to 1);
    y:out STD_LOGIC
    );
end mux_41;


--}} End of automatically maintained section

architecture mux41_behv of mux_41 is
begin
    process (s,i0,i1,i2,i3)
    begin
       
        case s is
            when "00" => y<= i0;
            when "01" => y<= i1;
            when "10" => y<= i2;
            when "11" => y<= i3;
           
            when others =>y<='X';
        end case;
    end process ;
   
       
     -- enter your statements here --

end mux41_behv;