vhdl program for 8x1 mux

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--
-- Title       : mux_81
-- Design      : and1
-- Author      : rajashekar
-- Company     : kits
--
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--
-- File        : mux_81.vhd
-- Generated   : Wed Jul 17 18:11:59 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description :
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {mux_81} architecture {mux81_behv}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_81 is
    port (i:in STD_LOGIC_VECTOR (0 to 7);
    s:in STD_LOGIC_VECTOR (0 to 2);
    y:out STD_LOGIC
    );
end mux_81;


--}} End of automatically maintained section

architecture mux81_behv of mux_81 is
begin
    process (i,s)
    begin
       
        case s is
            when "000" => y<= i(0);
            when "001" => y<= i(1);
            when "010" => y<= i(2);
            when "011" => y<= i(3);
            when "100" => y<= i(4);
            when "101" => y<= i(5);
            when "110" => y<= i(6);
            when "111" => y<= i(7);
           
            when others =>y<='X';
        end case;
    end process ;
   
       
     -- enter your statements here --

end mux81_behv;