vhdl program for all the basic gates

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--
-- Title       : full_adder
-- Design      : full_adder
-- Author      : rajashekar
-- Company     : kits
--
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--
-- File        : full_adder.vhd
-- Generated   : Tue Jun 18 16:48:04 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--                                                                                     y
-- Description :
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {and1} architecture {and1}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity and2 is
     port(
         a   : in STD_LOGIC;
         b   : in STD_LOGIC;
        c_and: out STD_LOGIC;
         c_or :out STD_LOGIC;
        c_nand:out STD_LOGIC;
         c_not:out STD_LOGIC;
         c_xor:out STD_LOGIC;
         c_xnor:out STD_LOGIC
       
         );
end and2;

--}} End of automatically maintained section

architecture and2_df of and2 is
begin   
    c_and <= a and b;
    c_or  <= a or b;
    c_nand<= a nand b;
    c_not <= not a;
    c_xor <= a xor b;
    c_xnor<= a xnor b;
   

end and2_df;