vhdl program for 2 input and gate

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity and_2 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c_and : out STD_LOGIC
         );
end and_2;

--}} End of automatically maintained section

architecture and_df of and_2 is
begin
   
    c_and <= a and b;

     -- enter your statements here --

end and_df;