vhdl program for 2 input nand gate

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--
-- Title       : nand_2
-- Design      : and1
-- Author      : rajashekar
-- Company     : kits
--
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--
-- File        : nand_2.vhd
-- Generated   : Sat Jun 29 14:17:43 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description :
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {nand_2} architecture {nand_df}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity nand_2 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c_nand : out STD_LOGIC
         );
end nand_2;

--}} End of automatically maintained section

architecture nand_df of nand_2 is
begin
   
    c_nand <= a nand b;

     -- enter your statements here --

end nand_df;