VHDL PROGRAM FOR HALF ADDER-USING NOR GATES

LIBrary IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity halfadd is
    port (a:in STD_LOGIC;
    b:in STD_LOGIC;
    hsum:out STD_LOGIC;
    hcarry:out STD_LOGIC );
end halfadd;

architecture halfadd_nor of halfadd is

component nor2 is
        port (a:in STD_LOGIC;
    b:in STD_LOGIC;
    c_nor:out std_logic );
end component ;   

signal s1,s2,s3,s4:std_logic;

begin
   
    x1:nor2 port map (a,b,s3);
    x2:nor2 port map (a,a,s1);
    x3:nor2 port map (b,b,s2);
    x4:nor2 port map (s1,s2,s4);
    x5:nor2 port map (s4,s3,hsum);   
    hcarry <= s4;
   
end halfadd_nor;