vhdl program for 2 input nor gate

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity or_2 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c_or : out STD_LOGIC
         );
end or_2;

--}} End of automatically maintained section

architecture or_df of or_2 is
begin
   
    c_or <= a or b;

     -- enter your statements here --

end or_df;